Ristretto: Random Test Generator for Multicore Microprocessor Cache Coherence Verification

Cache Coherence Verification with TLA+

We used the specification language TLA+ to analyze the correctness of two cache-coherence protocols for shared-memory multiprocessors based on two generations (EV6 and EV7) of the Alpha processor. A memory model defines the relationship between the values written by one processor and the values read by another, and a cache-coherence protocol manipulates the caches to preserve this relationship....

Guest Editors' Introduction: Microprocessor Test and Verification

millions of transistors operating at extraordinarily high speeds. Test and verification of these high-performance devices continuously challenge engineers in every microprocessor design cycle. This special issue presents state-of-the-art techniques for microprocessor test and verification. It aims to provide innovative ideas and new methodologies to solve the difficult challenges facing enginee...

Verification of the Futurebus+ Cache Coherence Protocol

We used a hardware description language to construct a formal model of the cache coherence protocol described in the draft IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found several errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group m...

Parameterized Cache Coherence Protocol Verification using Invariant

Verification of parameterized cache coherence protocol is very important in the share-memory multiprocessor system. In this paper, a new method was proposed to verify the correctness of parameterized cache coherence protocol based on the invariant. Firstly, we present the parameterized cache coherence protocol as semi-algebraic transition system, and then solve the invariant of transition syste...

TLA Verification of Cache-Coherence Protocols